module top(
           input clk,
           input rst_n,
           input data_in,
           output reg [7: 0] data_out
       );
reg [2: 0] cnt;
always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				data_out <= 8'b0;
				cnt <= 3'b0;
			end
		else
			begin
				data_out[cnt] <= data_in;
				cnt <= cnt + 1'b1;
			end
	end
always@(posedge clk or negedge rst_n)
	begin
		if (cnt == 3'd7)
			cnt <= 3'd0;
	end
endmodule
